The present invention relates generally to computer architectures and, in particular, to a computer architecture that allows “patching” of failed memory elements using alternative pre-existing memory.
The ability to fabricate processors using smaller transistors has allowed the construction of processors with greater transistor density and as a result many more transistors. Although the smaller transistors can have improved energy efficiency, generally the energy efficiency of each generation of smaller transistors lags behind the growth in transistor density. This leads to two distinct power dissipation problems: (1) the problem of “power density”, often leading to “local thermal hot-spots”, where a particular region of the chip consumes more power than can be quickly dissipated causing a rapid rise in temperature in that region, and (2) the problem of “global power dissipation” where the power consumed by the entire chip cannot be fully dissipated using cost-effective cooling methods.
These problems of power dissipation are generally addressed in two different ways. When performance is not critical, the operating voltage and clock speed of the processor may be reduced. Power consumption scales quadratically with supply voltage and so this approach allows for substantial power savings. Lower operating voltages can cause voltage-dependent errors in memory structures such as the processor cache.
An alternative approach is to push the temperature limits of the processors with the expectations of some levels of error. Higher operating temperatures can also cause temperature-dependent errors in memory structures such as the processor cache.
A variety of methods exist to mitigate temperature-dependent or voltage-dependent memory errors. For example, memory circuits can be redesigned to incorporate more components (for example, using eight transistor SRAM cells rather than six transistor SRAM cells) which provides decreased voltage and noise sensitivity. Alternatively or in addition, redundancy may be incorporated into the memory circuits, for example, using additional error correcting codes. Some errors can be mitigated by making the transistors of the memory circuits larger to reduce process variation that limits temperature or voltage reduction as dependent on “weakest link” memory cells.
Each of these techniques generally increase the size and hence the cost of the processor or memory structure.